Error Message Register Unloader Intel FPGA IP Core User Guide

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ID 683866
Date 5/23/2018
Public
Document Table of Contents
Document Table of Contents x
1. Error Message Register Unloader Intel® FPGA IP Core User Guide
1. Error Message Register Unloader Intel® FPGA IP Core User Guide x
1.1. Features 1.2. IP Core Device Support 1.3. Resource Utilization and Performance 1.4. Functional Description 1.5. Parameter Settings 1.6. Installing and Licensing Intel® FPGA IP Cores 1.7. Customizing and Generating IP Cores 1.8. Document Revision History for Error Message Register Unloader Intel® FPGA IP IP Core User Guide
1.4. Functional Description x
1.4.1. Error Message Register 1.4.2. Signals 1.4.3. Timing
1.4.3. Timing x
1.4.3.1. IP Timing Behavior ( Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices) 1.4.3.2. All Other Device Timing
1.7. Customizing and Generating IP Cores x
1.7.1. IP Catalog and Parameter Editor 1.7.2. The Parameter Editor 1.7.3. Specifying IP Core Parameters and Options 1.7.4. Specifying IP Core Parameters and Options (Legacy Parameter Editors)
1.7.3. Specifying IP Core Parameters and Options x
1.7.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
1.7.4. Specifying IP Core Parameters and Options (Legacy Parameter Editors) x
1.7.4.1. IP Core Generation Output ( Intel® Quartus® Prime Standard Edition)
1. Error Message Register Unloader Intel® FPGA IP Core User Guide

1.5. Parameter Settings

Table 4.   Error Message Register Unloader Parameters
Parameter Value Default Description
CRC error check clock divisor 1, 2, 4, 8, 16, 32, 64, 128, 256 2 Indicates the error detection clock divisor value to apply to the internal oscillator. The divided clock drives the internal CRC function. This setting must match the ERROR_CHECK_FREQUENCY_DIVISOR Intel® Quartus® Prime Settings File (.qsf) setting, otherwise the software issues a warning.

Stratix® IV and Arria® II devices do not support a value of 1.

Enable Virtual JTAG CRC error injection On, off Off Enables in-system sources and probes (ISSP) functionality to inject the EMR register content via the JTAG interface without changing the CRAM value. Use this interface to troubleshoot user logic that is connected to the core.
Input clock frequency Any 50 MHz Specifies the frequency of the Error Message Register Unloader IP core input clock. This option is applicable when the Input clock is driven from Internal Oscillator parameter is off.
Input clock is driven from Internal Oscillator On, off Off Indicates that the internal oscillator provides the core input clock. Enable this parameter if an internal oscillator drives the user design's core input clock.
Note: The frequency of the internal oscillator is not affected by the CRC error check clock divisor.
CRC Error Verify input clock frequency 10 - 50 MHz 50 MHz Specifies CRC Error Verify IP core (ALTERA_CRCERROR_VERIFY) input clock frequency.

Stratix® IV and Arria® II devices only.

Completion of full chip Error Detection cycle On, off Off Optional. Turn on to assert this signal at the end of each full chip error detection cycle.

Stratix® V, Intel® Arria® 10, Arria® V, Cyclone® V, and Intel® Cyclone® 10 GX devices only.

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