ALTERA DOES NOT WARRANT THAT THE FUNCTIONS CONTAINED IN THIS PATCH 
WILL MEET YOUR REQUIREMENTS, OR THAT THE OPERATION OF THIS PATCH 
WILL BE UNINTERRUPTED OR ERROR-FREE. 

//**************************************************************** 
readme_patch_9.1_2.73.txt 
Readme file for Quartus II 9.1 Patch 2.73 
Copyright (C) Altera Corporation 2010 All right reserved. 
Patch created on June 25 2010
Patch SPR#: 346328 
SPRs fixed: 345382
//**************************************************************** 

Problem:  Stratix III DDR input registers fail to capture edge-aligned
	  input data correctly while TimeQuest shows positive slack
	  when corner clock pin and corner PLL are used.


Solution: The path from corner clock pin to corner PLL has incorrect
          delay and the patch updates the delay.  Designs utilizing
          the affected path on the affected Stratix III parts will
          need to re-run TimeQuest Timing Analyzer.  If new timing
          violations occur, user will need to re-run fit.
  	  

Parts Affected: Stratix III EP3SL200F1517, EP3SE260F1517, EP3SL340F1517, 
	  EP3SL340F1760


Designs Affected: Any design with corner PLL (PLL_L1, PLL_L4, PLL_R1, PLL_R4) 
	  driven by corner clock pins.


Caution - You must either have previously installed the Quartus II 
          software version 9.1 SP2 or must install the Quartus II 
          software version 9.1 SP2 before installing this patch. 
          Otherwise, the patch will not be installed correctly and 
          the Quartus II software will not run properly.