hyperram_q_sys

2017.08.03.14:48:19 Datasheet
Overview
  mSGDMA_0_clk  hyperram_q_sys

All Components
   mSGDMA_0 mSGDMA 1.0
   mSGDMA_0_dispatcher_read modular_sgdma_dispatcher 17.0
   mSGDMA_0_dispatcher_write modular_sgdma_dispatcher 17.0
   mSGDMA_0_freq_counter_0 freq_counter 1.0
   mSGDMA_0_mm_bridge_slv altera_avalon_mm_bridge 17.0
   mSGDMA_0_prbs_pattern_checker prbs_pattern_checker 1.1
   mSGDMA_0_prbs_pattern_generator prbs_pattern_generator 1.1
   mSGDMA_0_timer_0 altera_avalon_timer 17.0
   master_driver_msgdma_0 master_driver_msgdma 1.0
   product_info_0 product_info 1.0
   sll_hyperbus_controller_top_0 sll_hyperbus_controller_top 2.14.4
Memory Map
mSGDMA_0 mSGDMA_0_dma_read_master mSGDMA_0_dma_write_master master_0 master_driver_msgdma_0
 dma_read_master  dma_write_master  Data_Read_Master  Data_Write_Master  master  avalon_master
  mSGDMA_0
mm_bridge_slv 
  mSGDMA_0_dispatcher_read
CSR  0x00200080
Descriptor_Slave  0x002000b0
  mSGDMA_0_dispatcher_write
CSR  0x00200060
Descriptor_Slave  0x002000a0
  mSGDMA_0_freq_counter_0
csr  0x00200140
  mSGDMA_0_prbs_pattern_checker
csr  0x00200000
  mSGDMA_0_prbs_pattern_generator
csr  0x00200040
  mSGDMA_0_timer_0
s1  0x00200100
  master_driver_msgdma_0
csr  0x00100000
  product_info_0
avalon_slave_0  0x00000000
  sll_hyperbus_controller_top_0
iavs0  0x00000000 0x00000000 0x00000000 0x00000000

mSGDMA_0

mSGDMA v1.0


Parameters

AUTO_GENERATION_ID 1501742898
AUTO_UNIQUE_ID hyperram_q_sys_mSGDMA_0
AUTO_DEVICE_FAMILY CYCLONE10LP
AUTO_DEVICE 10CL025YU256I7G
AUTO_DEVICE_SPEEDGRADE 7
AUTO_CLK_CLOCK_RATE 100000000
AUTO_CLK_CLOCK_DOMAIN 4
AUTO_CLK_RESET_DOMAIN 4
AUTO_DMA_READ_MASTER_ADDRESS_MAP <address-map><slave name='sll_hyperbus_controller_top_0.iavs0' start='0x0' end='0x1000000' /></address-map>
AUTO_DMA_READ_MASTER_ADDRESS_WIDTH AddressWidth = 24
AUTO_DMA_WRITE_MASTER_ADDRESS_MAP <address-map><slave name='sll_hyperbus_controller_top_0.iavs0' start='0x0' end='0x1000000' /></address-map>
AUTO_DMA_WRITE_MASTER_ADDRESS_WIDTH AddressWidth = 24
deviceFamily Cyclone 10 LP
generateLegacySim false
  

Software Assignments

(none)

mSGDMA_0_clk

clock_source v17.0
sll_hyperbus_controller_top_0 o_av_out_clk   mSGDMA_0_clk
  clk_in
o_av_out_rstn  
  clk_in_reset
master_driver_msgdma_0 reset_source  
  clk_in_reset
clk   mSGDMA_0_dma_read_master
  Clock
clk_reset  
  Clock_reset
clk   mSGDMA_0_dma_write_master
  Clock
clk_reset  
  Clock_reset
clk   mSGDMA_0_timing_adapter
  clk
clk_reset  
  reset
clk   mSGDMA_0_mm_bridge_slv
  clk
clk_reset  
  reset
clk   mSGDMA_0_timer_0
  clk
clk_reset  
  reset
clk   mSGDMA_0_dispatcher_read
  clock
clk_reset  
  clock_reset
clk   mSGDMA_0_prbs_pattern_checker
  clock
clk_reset  
  reset
clk   mSGDMA_0_dispatcher_write
  clock
clk_reset  
  clock_reset
clk   mSGDMA_0_prbs_pattern_generator
  clock
clk_reset  
  reset
clk   mSGDMA_0_freq_counter_0
  clock
clk  
  sample_clock
clk_reset  
  reset


Parameters

clockFrequency 75000000
clockFrequencyKnown true
inputClockFrequency 100000000
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

mSGDMA_0_dispatcher_read

modular_sgdma_dispatcher v17.0
mSGDMA_0_mm_bridge_slv m0   mSGDMA_0_dispatcher_read
  CSR
m0  
  Descriptor_Slave
mSGDMA_0_dma_read_master Response_Source  
  Read_Response_Sink
mSGDMA_0_clk clk  
  clock
clk_reset  
  clock_reset
master_driver_msgdma_0 interrupt_receiver  
  csr_irq
Read_Command_Source   mSGDMA_0_dma_read_master
  Command_Sink


Parameters

PREFETCHER_USE_CASE 0
MODE 1
GUI_RESPONSE_PORT 0
RESPONSE_PORT 2
DESCRIPTOR_INTERFACE 0
DESCRIPTOR_FIFO_DEPTH 1024
ENHANCED_FEATURES 0
DESCRIPTOR_WIDTH 128
DESCRIPTOR_BYTEENABLE_WIDTH 16
CSR_ADDRESS_WIDTH 3
DATA_WIDTH 32
DATA_FIFO_DEPTH 32
MAX_BYTE 1024
TRANSFER_TYPE Aligned Accesses
BURST_ENABLE 0
MAX_BURST_COUNT 2
BURST_WRAPPING_SUPPORT 0
STRIDE_ENABLE 0
MAX_STRIDE 1
PROGRAMMABLE_BURST_ENABLE 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BURST_ENABLE 0
BURST_WRAPPING_SUPPORT 0
DATA_FIFO_DEPTH 32
DATA_WIDTH 32
DESCRIPTOR_FIFO_DEPTH 1024
ENHANCED_FEATURES 0
MAX_BURST_COUNT 2
MAX_BYTE 1024
MAX_STRIDE 1
PROGRAMMABLE_BURST_ENABLE 0
RESPONSE_FIFO_DEPTH 2048
RESPONSE_PORT 0
STRIDE_ENABLE 0
TRANSFER_TYPE Aligned Accesses

mSGDMA_0_dispatcher_write

modular_sgdma_dispatcher v17.0
mSGDMA_0_mm_bridge_slv m0   mSGDMA_0_dispatcher_write
  CSR
m0  
  Descriptor_Slave
mSGDMA_0_dma_write_master Response_Source  
  Write_Response_Sink
mSGDMA_0_clk clk  
  clock
clk_reset  
  clock_reset
master_driver_msgdma_0 interrupt_receiver  
  csr_irq
Write_Command_Source   mSGDMA_0_dma_write_master
  Command_Sink


Parameters

PREFETCHER_USE_CASE 0
MODE 2
GUI_RESPONSE_PORT 2
RESPONSE_PORT 2
DESCRIPTOR_INTERFACE 0
DESCRIPTOR_FIFO_DEPTH 1024
ENHANCED_FEATURES 0
DESCRIPTOR_WIDTH 128
DESCRIPTOR_BYTEENABLE_WIDTH 16
CSR_ADDRESS_WIDTH 3
DATA_WIDTH 32
DATA_FIFO_DEPTH 32
MAX_BYTE 1024
TRANSFER_TYPE Aligned Accesses
BURST_ENABLE 0
MAX_BURST_COUNT 2
BURST_WRAPPING_SUPPORT 0
STRIDE_ENABLE 0
MAX_STRIDE 1
PROGRAMMABLE_BURST_ENABLE 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BURST_ENABLE 0
BURST_WRAPPING_SUPPORT 0
DATA_FIFO_DEPTH 32
DATA_WIDTH 32
DESCRIPTOR_FIFO_DEPTH 1024
ENHANCED_FEATURES 0
MAX_BURST_COUNT 2
MAX_BYTE 1024
MAX_STRIDE 1
PROGRAMMABLE_BURST_ENABLE 0
RESPONSE_FIFO_DEPTH 2048
RESPONSE_PORT 2
STRIDE_ENABLE 0
TRANSFER_TYPE Aligned Accesses

mSGDMA_0_dma_read_master

dma_read_master v17.0
mSGDMA_0_dispatcher_read Read_Command_Source   mSGDMA_0_dma_read_master
  Command_Sink
mSGDMA_0_clk clk  
  Clock
clk_reset  
  Clock_reset
Data_Source   mSGDMA_0_prbs_pattern_checker
  st_pattern_input
Response_Source   mSGDMA_0_dispatcher_read
  Read_Response_Sink
Data_Read_Master   sll_hyperbus_controller_top_0
  iavs0


Parameters

DATA_WIDTH 32
LENGTH_WIDTH 25
FIFO_DEPTH 1024
USE_FIX_ADDRESS_WIDTH 0
FIX_ADDRESS_WIDTH 32
STRIDE_ENABLE 0
GUI_STRIDE_WIDTH 1
BURST_ENABLE 1
GUI_MAX_BURST_COUNT 8
GUI_PROGRAMMABLE_BURST_ENABLE 0
GUI_BURST_WRAPPING_SUPPORT 1
TRANSFER_TYPE Full Word Accesses Only
PACKET_ENABLE 0
ERROR_ENABLE 0
ERROR_WIDTH 8
CHANNEL_ENABLE 0
CHANNEL_WIDTH 8
BYTE_ENABLE_WIDTH 4
BYTE_ENABLE_WIDTH_LOG2 2
AUTO_ADDRESS_WIDTH 24
ADDRESS_WIDTH 24
FIFO_DEPTH_LOG2 10
SYMBOL_WIDTH 8
NUMBER_OF_SYMBOLS 4
NUMBER_OF_SYMBOLS_LOG2 2
MAX_BURST_COUNT_WIDTH 4
UNALIGNED_ACCESSES_ENABLE 0
ONLY_FULL_ACCESS_ENABLE 1
BURST_WRAPPING_SUPPORT 1
PROGRAMMABLE_BURST_ENABLE 0
MAX_BURST_COUNT 8
FIFO_SPEED_OPTIMIZATION 1
STRIDE_WIDTH 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

mSGDMA_0_dma_write_master

dma_write_master v17.0
mSGDMA_0_dispatcher_write Write_Command_Source   mSGDMA_0_dma_write_master
  Command_Sink
mSGDMA_0_timing_adapter out  
  Data_Sink
mSGDMA_0_clk clk  
  Clock
clk_reset  
  Clock_reset
Response_Source   mSGDMA_0_dispatcher_write
  Write_Response_Sink
Data_Write_Master   sll_hyperbus_controller_top_0
  iavs0


Parameters

DATA_WIDTH 32
LENGTH_WIDTH 25
FIFO_DEPTH 1024
USE_FIX_ADDRESS_WIDTH 0
FIX_ADDRESS_WIDTH 32
STRIDE_ENABLE 0
GUI_STRIDE_WIDTH 1
BURST_ENABLE 1
GUI_MAX_BURST_COUNT 8
GUI_PROGRAMMABLE_BURST_ENABLE 0
GUI_BURST_WRAPPING_SUPPORT 1
TRANSFER_TYPE Full Word Accesses Only
PACKET_ENABLE 0
ERROR_ENABLE 0
ERROR_WIDTH 8
BYTE_ENABLE_WIDTH 4
BYTE_ENABLE_WIDTH_LOG2 2
AUTO_ADDRESS_WIDTH 24
ADDRESS_WIDTH 24
FIFO_DEPTH_LOG2 10
SYMBOL_WIDTH 8
NUMBER_OF_SYMBOLS 4
NUMBER_OF_SYMBOLS_LOG2 2
MAX_BURST_COUNT_WIDTH 4
UNALIGNED_ACCESSES_ENABLE 0
ONLY_FULL_ACCESS_ENABLE 1
BURST_WRAPPING_SUPPORT 1
PROGRAMMABLE_BURST_ENABLE 0
MAX_BURST_COUNT 8
FIFO_SPEED_OPTIMIZATION 1
STRIDE_WIDTH 1
ACTUAL_BYTES_TRANSFERRED_WIDTH 32
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

mSGDMA_0_freq_counter_0

freq_counter v1.0
mSGDMA_0_mm_bridge_slv m0   mSGDMA_0_freq_counter_0
  csr
mSGDMA_0_clk clk  
  clock
clk  
  sample_clock
clk_reset  
  reset


Parameters

SYSTEM_CLK_FREQ_PICO_SEC 13333
DIV 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

mSGDMA_0_mm_bridge_slv

altera_avalon_mm_bridge v17.0
mSGDMA_0_clk clk   mSGDMA_0_mm_bridge_slv
  clk
clk_reset  
  reset
master_driver_msgdma_0 avalon_master  
  s0
m0   mSGDMA_0_dispatcher_write
  CSR
m0  
  Descriptor_Slave
m0   mSGDMA_0_dispatcher_read
  CSR
m0  
  Descriptor_Slave
m0   mSGDMA_0_prbs_pattern_generator
  csr
m0   mSGDMA_0_prbs_pattern_checker
  csr
m0   mSGDMA_0_freq_counter_0
  csr
m0   mSGDMA_0_timer_0
  s1


Parameters

DATA_WIDTH 32
SYMBOL_WIDTH 8
ADDRESS_WIDTH 20
SYSINFO_ADDR_WIDTH 9
USE_AUTO_ADDRESS_WIDTH 1
AUTO_ADDRESS_WIDTH 9
HDL_ADDR_WIDTH 9
ADDRESS_UNITS SYMBOLS
BURSTCOUNT_WIDTH 4
MAX_BURST_SIZE 8
MAX_PENDING_RESPONSES 16
LINEWRAPBURSTS 0
PIPELINE_COMMAND 1
PIPELINE_RESPONSE 1
USE_RESPONSE 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

mSGDMA_0_prbs_pattern_checker

prbs_pattern_checker v1.1
mSGDMA_0_mm_bridge_slv m0   mSGDMA_0_prbs_pattern_checker
  csr
mSGDMA_0_dma_read_master Data_Source  
  st_pattern_input
mSGDMA_0_clk clk  
  clock
clk_reset  
  reset


Parameters

DATA_WIDTH 32
PRBS_WIDTH 16
AUTO_CLOCK_CLOCK_RATE 100000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

mSGDMA_0_prbs_pattern_generator

prbs_pattern_generator v1.1
mSGDMA_0_mm_bridge_slv m0   mSGDMA_0_prbs_pattern_generator
  csr
mSGDMA_0_clk clk  
  clock
clk_reset  
  reset
st_pattern_output   mSGDMA_0_timing_adapter
  in


Parameters

DATA_WIDTH 32
PRBS_WIDTH 16
AUTO_CLOCK_CLOCK_RATE 100000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

mSGDMA_0_timer_0

altera_avalon_timer v17.0
mSGDMA_0_mm_bridge_slv m0   mSGDMA_0_timer_0
  s1
mSGDMA_0_clk clk  
  clk
clk_reset  
  reset


Parameters

alwaysRun false
counterSize 32
fixedPeriod false
period 1
periodUnits MSEC
resetOutput false
snapshot true
timeoutPulseOutput false
systemFrequency 100000000
watchdogPulse 2
timerPreset FULL_FEATURED
periodUnitsString ms
valueInSecond 0.001
loadValue 99999
mult 0.001
ticksPerSec 1000.0
slave_address_width 3
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

ALWAYS_RUN 0
COUNTER_SIZE 32
FIXED_PERIOD 0
FREQ 100000000
LOAD_VALUE 99999
MULT 0.001
PERIOD 1
PERIOD_UNITS ms
RESET_OUTPUT 0
SNAPSHOT 1
TICKS_PER_SEC 1000
TIMEOUT_PULSE_OUTPUT 0

mSGDMA_0_timing_adapter

timing_adapter v17.0
mSGDMA_0_prbs_pattern_generator st_pattern_output   mSGDMA_0_timing_adapter
  in
mSGDMA_0_clk clk  
  clk
clk_reset  
  reset
out   mSGDMA_0_dma_write_master
  Data_Sink


Parameters

inChannelWidth 0
inMaxChannel 0
inBitsPerSymbol 8
inUsePackets false
inUseEmptyPort AUTO
inUseEmpty false
inSymbolsPerBeat 4
inUseReady true
outUseReady true
inReadyLatency 1
outReadyLatency 0
inErrorWidth 0
inErrorDescriptor
inUseValid true
outUseValid true
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

master_0

altera_jtag_avalon_master v17.0
sll_hyperbus_controller_top_0 o_av_out_clk   master_0
  clk
o_av_out_rstn  
  clk_reset
master   product_info_0
  avalon_slave_0
master   master_driver_msgdma_0
  csr


Parameters

USE_PLI 0
PLI_PORT 50000
COMPONENT_CLOCK 0
FAST_VER 0
FIFO_DEPTHS 2
AUTO_DEVICE_FAMILY CYCLONE10LP
AUTO_DEVICE 10CL025YU256I7G
AUTO_DEVICE_SPEEDGRADE 7
deviceFamily Cyclone 10 LP
generateLegacySim false
  

Software Assignments

(none)

master_driver_msgdma_0

master_driver_msgdma v1.0
master_0 master   master_driver_msgdma_0
  csr
sll_hyperbus_controller_top_0 o_av_out_clk  
  clock
o_av_out_rstn  
  reset
avalon_master   mSGDMA_0_mm_bridge_slv
  s0
interrupt_receiver   mSGDMA_0_dispatcher_read
  csr_irq
interrupt_receiver   mSGDMA_0_dispatcher_write
  csr_irq
reset_source   mSGDMA_0_clk
  clk_in_reset


Parameters

PRBS_PATTERN_GENERATOR_BASE 2097216
PRBS_PATTERN_CHECKER_BASE 2097152
MEMORY_BASE_ADDRESS 0
MEMORY_SPAN 8388608
BLOCK_SIZE 256
DISPATCHER_WRITE_CSR 2097248
DISPATCHER_WRITE_DESCRIPTOR 2097312
DISPATCHER_READ_CSR 2097280
DISPATCHER_READ_DESCRIPTOR 2097328
TIMER_BASE 2097408
FREQUENCY_COUNTER_BASE 2097472
ENABLE_PER_INFO 1
LOCAL_DATA_WORDS 4
AUTO_INTERRUPT_RECEIVER_INTERRUPTS_USED 3
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

product_info_0

product_info v1.0
master_0 master   product_info_0
  avalon_slave_0
sll_hyperbus_controller_top_0 o_av_out_clk  
  clock_reset
o_av_out_rstn  
  clock_reset_reset


Parameters

AUTO_DEVICE_FAMILY CYCLONE10LP
AUTO_CLOCK_RESET_CLOCK_RATE 100000000
deviceFamily Cyclone 10 LP
generateLegacySim false
  

Software Assignments

(none)

sll_hyperbus_controller_top_0

sll_hyperbus_controller_top v2.14.4
mSGDMA_0_dma_read_master Data_Read_Master   sll_hyperbus_controller_top_0
  iavs0
mSGDMA_0_dma_write_master Data_Write_Master  
  iavs0
o_av_out_clk   master_0
  clk
o_av_out_rstn  
  clk_reset
o_av_out_clk   mSGDMA_0_clk
  clk_in
o_av_out_rstn  
  clk_in_reset
o_av_out_clk   master_driver_msgdma_0
  clock
o_av_out_rstn  
  reset
o_av_out_clk   product_info_0
  clock_reset
o_av_out_rstn  
  clock_reset_reset


Parameters

EVAL_MODE true
GUI_INCLUDE_IO_PADS 1
GUI_FPGA_DEV_BOARD alt_c10_dev2
NUM_CHIPSELECTS 2
GUI_NUM_CHIPSELECTS 2
GUI_INCLUDE_REG_AVALON 0
GUI_NUMBER_OF_MEM_ACCESS_PORTS 1
GUI_IAVS0_RWBUFFER_CONFIG 0
GUI_INPUT_FREQ_IN_MHZ_BOARD 50
GUI_INPUT_FREQ_IN_MHZ_MANUAL 50
GUI_INPUT_FREQ_IN_MHZ_SC 50
GUI_IAVS0_AUTO_CLOCK_RATE 100000000
GUI_I_HYPERBUS_AUTO_CLOCK_RATE 0
GUI_SINGLE_CLK_OP true
HYPERBUS_FREQ_IN_MHZ 100
IAVS_FREQ_OUT_IN_MHZ 75
GUI_IAVS0_BANDWIDTH_IN_MBS_SC 400
GUI_HYPERBUS_BANDWIDTH_IN_MBS_SC 200
GUI_AV_OUT_FREQ_IN_MHZ_SC 100
GUI_IAVSR_FREQ_IN_MHZ_SC 100
GUI_IAVS0_FREQ_IN_MHZ_SC 100
GUI_IAVS0_CLOCK_CROSSING_SC Direct passthrough without clock crossing logic
GUI_HYPERBUS_FREQ_IN_MHZ_SC 100
GUI_IAVS0_WRITE_MODE true
GUI_IAVS0_BYTEENABLE true
GUI_IAVS0_PORT_MODE Read/Write
GUI_IAVS0_REG_WDATA true
GUI_IAVS0_REG_RDATA true
GUI_IAVS0_USE_RESPONSE false
GUI_IAVS0_MAX_BURST_IN_WORDS 8
GUI_IAVS0_LINEWRAP_BURST false
GUI_IAVS0_BURST_ON_BURST_BOUNDARIES_ONLY true
GUI_IAVS0_BURST_ON_BURST_BOUNDARIES_AUTO true
GUI_IAVS0_DATA_WIDTH 32
GUI_IAVS0_ADDR_WIDTH 23
GUI_IAVS0_ADDR_UNITS Words
GUI_DEV0_TYPE_MAN none
GUI_DEV0_TYPE none
GUI_DEV0_USE_DEFAULT true
GUI_DEV0_DRIVE_STRENGTH_MAN 0
GUI_DEV0_DRIVE_STRENGTH 0
GUI_DEV0_INIT_LATENCY_MAN 6
GUI_DEV0_INIT_LATENCY 16
GUI_DEV0_FIXED_LATENCY_MAN 1
GUI_DEV0_FIXED_LATENCY 1
GUI_DEV0_BURST_LENGTH_MAN 3
GUI_DEV0_BURST_LENGTH 3
GUI_DEV0_NAME No device connected and/or configured for use
GUI_DEV0_SIZE 0
GUI_DEV0_MIN_TACC 16
GUI_DEV0_T_ACC 0
GUI_DEV0_T_RWR 0
GUI_DEV0_T_CSHI 0
GUI_DEV0_T_CSS 0
GUI_DEV0_T_CSH 0
GUI_DEV1_TYPE_MAN none
GUI_DEV1_TYPE is66wvh16m8
GUI_DEV1_USE_DEFAULT true
GUI_DEV1_DRIVE_STRENGTH_MAN 0
GUI_DEV1_DRIVE_STRENGTH 0
GUI_DEV1_INIT_LATENCY_MAN 6
GUI_DEV1_INIT_LATENCY 6
GUI_DEV1_FIXED_LATENCY_MAN 1
GUI_DEV1_FIXED_LATENCY 1
GUI_DEV1_BURST_LENGTH_MAN 3
GUI_DEV1_BURST_LENGTH 3
GUI_DEV1_NAME IS66WVH16M8 - ISSI - HyperRAM - 166 MHz - 128 Mbit
GUI_DEV1_SIZE 16
GUI_DEV1_MIN_TACC 4
GUI_DEV1_T_ACC 6
GUI_DEV1_T_RWR 4
GUI_DEV1_T_CSHI 1
GUI_DEV1_T_CSS 1
GUI_DEV1_T_CSH 1
DEVICE_FAMILY CYCLONE10LP
g_iavs0_addr_width 23
g_iavs0_data_width 32
g_iavs0_av_numsymbols 4
g_iavs0_burstcount_width 4
g_iavs0_linewrap_burst 1
g_iavs0_register_rdata 1
g_iavs0_register_wdata 1
g_include_reg_avalon 0
g_input_clk_freq_in_mhz 50
g_hyperbus_freq_in_mhz 100
g_iavs_freq_in_mhz 100
g_same_iavs_hyperbus_clk 1
g_config_rd_buffer_as_sram 0
g_config_wr_buffer_as_sram 0
g_device_family Cyclone 10 LP
g_num_chipselect 2
g_dev0_config 0
g_dev1_config 2401173569
g_dev0_timing 0
g_dev1_timing 409873
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)
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