hyperram_q_sys |
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2017.08.03.14:48:19 | Datasheet |
mSGDMA_0_clk | hyperram_q_sys |
mSGDMA_0 | mSGDMA_0_dma_read_master | mSGDMA_0_dma_write_master | master_0 | master_driver_msgdma_0 | ||
dma_read_master | dma_write_master | Data_Read_Master | Data_Write_Master | master | avalon_master | |
mSGDMA_0 | ||||||
mm_bridge_slv | ||||||
mSGDMA_0_dispatcher_read | ||||||
CSR | 0x00200080 | |||||
Descriptor_Slave | 0x002000b0 | |||||
mSGDMA_0_dispatcher_write | ||||||
CSR | 0x00200060 | |||||
Descriptor_Slave | 0x002000a0 | |||||
mSGDMA_0_freq_counter_0 | ||||||
csr | 0x00200140 | |||||
mSGDMA_0_prbs_pattern_checker | ||||||
csr | 0x00200000 | |||||
mSGDMA_0_prbs_pattern_generator | ||||||
csr | 0x00200040 | |||||
mSGDMA_0_timer_0 | ||||||
s1 | 0x00200100 | |||||
master_driver_msgdma_0 | ||||||
csr | 0x00100000 | |||||
product_info_0 | ||||||
avalon_slave_0 | 0x00000000 | |||||
sll_hyperbus_controller_top_0 | ||||||
iavs0 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 |
Parameters
|
Software Assignments(none) |
sll_hyperbus_controller_top_0 | o_av_out_clk | mSGDMA_0_clk | |
clk_in | |||
o_av_out_rstn | |||
clk_in_reset | |||
master_driver_msgdma_0 | reset_source | ||
clk_in_reset | |||
clk | mSGDMA_0_dma_read_master | ||
Clock | |||
clk_reset | |||
Clock_reset | |||
clk | mSGDMA_0_dma_write_master | ||
Clock | |||
clk_reset | |||
Clock_reset | |||
clk | mSGDMA_0_timing_adapter | ||
clk | |||
clk_reset | |||
reset | |||
clk | mSGDMA_0_mm_bridge_slv | ||
clk | |||
clk_reset | |||
reset | |||
clk | mSGDMA_0_timer_0 | ||
clk | |||
clk_reset | |||
reset | |||
clk | mSGDMA_0_dispatcher_read | ||
clock | |||
clk_reset | |||
clock_reset | |||
clk | mSGDMA_0_prbs_pattern_checker | ||
clock | |||
clk_reset | |||
reset | |||
clk | mSGDMA_0_dispatcher_write | ||
clock | |||
clk_reset | |||
clock_reset | |||
clk | mSGDMA_0_prbs_pattern_generator | ||
clock | |||
clk_reset | |||
reset | |||
clk | mSGDMA_0_freq_counter_0 | ||
clock | |||
clk | |||
sample_clock | |||
clk_reset | |||
reset |
Parameters
|
Software Assignments(none) |
mSGDMA_0_mm_bridge_slv | m0 | mSGDMA_0_dispatcher_read | |
CSR | |||
m0 | |||
Descriptor_Slave | |||
mSGDMA_0_dma_read_master | Response_Source | ||
Read_Response_Sink | |||
mSGDMA_0_clk | clk | ||
clock | |||
clk_reset | |||
clock_reset | |||
master_driver_msgdma_0 | interrupt_receiver | ||
csr_irq | |||
Read_Command_Source | mSGDMA_0_dma_read_master | ||
Command_Sink |
Parameters
|
Software Assignments
|
mSGDMA_0_mm_bridge_slv | m0 | mSGDMA_0_dispatcher_write | |
CSR | |||
m0 | |||
Descriptor_Slave | |||
mSGDMA_0_dma_write_master | Response_Source | ||
Write_Response_Sink | |||
mSGDMA_0_clk | clk | ||
clock | |||
clk_reset | |||
clock_reset | |||
master_driver_msgdma_0 | interrupt_receiver | ||
csr_irq | |||
Write_Command_Source | mSGDMA_0_dma_write_master | ||
Command_Sink |
Parameters
|
Software Assignments
|
mSGDMA_0_dispatcher_read | Read_Command_Source | mSGDMA_0_dma_read_master | |
Command_Sink | |||
mSGDMA_0_clk | clk | ||
Clock | |||
clk_reset | |||
Clock_reset | |||
Data_Source | mSGDMA_0_prbs_pattern_checker | ||
st_pattern_input | |||
Response_Source | mSGDMA_0_dispatcher_read | ||
Read_Response_Sink | |||
Data_Read_Master | sll_hyperbus_controller_top_0 | ||
iavs0 |
Parameters
|
Software Assignments(none) |
mSGDMA_0_dispatcher_write | Write_Command_Source | mSGDMA_0_dma_write_master | |
Command_Sink | |||
mSGDMA_0_timing_adapter | out | ||
Data_Sink | |||
mSGDMA_0_clk | clk | ||
Clock | |||
clk_reset | |||
Clock_reset | |||
Response_Source | mSGDMA_0_dispatcher_write | ||
Write_Response_Sink | |||
Data_Write_Master | sll_hyperbus_controller_top_0 | ||
iavs0 |
Parameters
|
Software Assignments(none) |
mSGDMA_0_mm_bridge_slv | m0 | mSGDMA_0_freq_counter_0 |
csr | ||
mSGDMA_0_clk | clk | |
clock | ||
clk | ||
sample_clock | ||
clk_reset | ||
reset |
Parameters
|
Software Assignments(none) |
mSGDMA_0_clk | clk | mSGDMA_0_mm_bridge_slv | |
clk | |||
clk_reset | |||
reset | |||
master_driver_msgdma_0 | avalon_master | ||
s0 | |||
m0 | mSGDMA_0_dispatcher_write | ||
CSR | |||
m0 | |||
Descriptor_Slave | |||
m0 | mSGDMA_0_dispatcher_read | ||
CSR | |||
m0 | |||
Descriptor_Slave | |||
m0 | mSGDMA_0_prbs_pattern_generator | ||
csr | |||
m0 | mSGDMA_0_prbs_pattern_checker | ||
csr | |||
m0 | mSGDMA_0_freq_counter_0 | ||
csr | |||
m0 | mSGDMA_0_timer_0 | ||
s1 |
Parameters
|
Software Assignments(none) |
mSGDMA_0_mm_bridge_slv | m0 | mSGDMA_0_prbs_pattern_checker |
csr | ||
mSGDMA_0_dma_read_master | Data_Source | |
st_pattern_input | ||
mSGDMA_0_clk | clk | |
clock | ||
clk_reset | ||
reset |
Parameters
|
Software Assignments(none) |
mSGDMA_0_mm_bridge_slv | m0 | mSGDMA_0_prbs_pattern_generator | |
csr | |||
mSGDMA_0_clk | clk | ||
clock | |||
clk_reset | |||
reset | |||
st_pattern_output | mSGDMA_0_timing_adapter | ||
in |
Parameters
|
Software Assignments(none) |
mSGDMA_0_mm_bridge_slv | m0 | mSGDMA_0_timer_0 |
s1 | ||
mSGDMA_0_clk | clk | |
clk | ||
clk_reset | ||
reset |
Parameters
|
Software Assignments
|
mSGDMA_0_prbs_pattern_generator | st_pattern_output | mSGDMA_0_timing_adapter | |
in | |||
mSGDMA_0_clk | clk | ||
clk | |||
clk_reset | |||
reset | |||
out | mSGDMA_0_dma_write_master | ||
Data_Sink |
Parameters
|
Software Assignments(none) |
sll_hyperbus_controller_top_0 | o_av_out_clk | master_0 | |
clk | |||
o_av_out_rstn | |||
clk_reset | |||
master | product_info_0 | ||
avalon_slave_0 | |||
master | master_driver_msgdma_0 | ||
csr |
Parameters
|
Software Assignments(none) |
master_0 | master | master_driver_msgdma_0 | |
csr | |||
sll_hyperbus_controller_top_0 | o_av_out_clk | ||
clock | |||
o_av_out_rstn | |||
reset | |||
avalon_master | mSGDMA_0_mm_bridge_slv | ||
s0 | |||
interrupt_receiver | mSGDMA_0_dispatcher_read | ||
csr_irq | |||
interrupt_receiver | mSGDMA_0_dispatcher_write | ||
csr_irq | |||
reset_source | mSGDMA_0_clk | ||
clk_in_reset |
Parameters
|
Software Assignments(none) |
master_0 | master | product_info_0 |
avalon_slave_0 | ||
sll_hyperbus_controller_top_0 | o_av_out_clk | |
clock_reset | ||
o_av_out_rstn | ||
clock_reset_reset |
Parameters
|
Software Assignments(none) |
mSGDMA_0_dma_read_master | Data_Read_Master | sll_hyperbus_controller_top_0 | |
iavs0 | |||
mSGDMA_0_dma_write_master | Data_Write_Master | ||
iavs0 | |||
o_av_out_clk | master_0 | ||
clk | |||
o_av_out_rstn | |||
clk_reset | |||
o_av_out_clk | mSGDMA_0_clk | ||
clk_in | |||
o_av_out_rstn | |||
clk_in_reset | |||
o_av_out_clk | master_driver_msgdma_0 | ||
clock | |||
o_av_out_rstn | |||
reset | |||
o_av_out_clk | product_info_0 | ||
clock_reset | |||
o_av_out_rstn | |||
clock_reset_reset |
Parameters
|
Software Assignments(none) |
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