ctrlcfg4

         
      
Module Instance Base Address Register Address
i_io48_hmc_mmr_io48_mmr 0xFFCFA000 0xFFCFA038

Offset: 0x38

Access: RW

Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

cfg_dbc3_slot_offset

0x0

cfg_dbc2_slot_offset

0x0

cfg_dbc1_slot_offset

0x0

cfg_dbc0_slot_offset

0x0

cfg_ctrl_slot_offset

0x0

cfg_dbc3_slot_rotate_en

0x0

cfg_dbc2_slot_rotate_en

0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_dbc1_slot_rotate_en

0x0

cfg_dbc0_slot_rotate_en

0x0

cfg_ctrl_slot_rotate_en

0x0

cfg_pingpong_mode

0x0

cfg_tile_id

0x0

ctrlcfg4 Fields

Bit Name Description Access Reset
31:30 cfg_dbc3_slot_offset
Enables afi information to be offset by numbers of FR cycles. Affected afi signal is afi_rdata_en, afi_rdata_en_full, afi_wdata_valid, afi_dqs_burst, afi_mrnk_write and afi_mrnk_read. Set this to: - 2
RW 0x0
29:28 cfg_dbc2_slot_offset
Enables afi information to be offset by numbers of FR cycles. Affected afi signal is afi_rdata_en, afi_rdata_en_full, afi_wdata_valid, afi_dqs_burst, afi_mrnk_write and afi_mrnk_read. Set this to: - 2
RW 0x0
27:26 cfg_dbc1_slot_offset
Enables afi information to be offset by numbers of FR cycles. Affected afi signal is afi_rdata_en, afi_rdata_en_full, afi_wdata_valid, afi_dqs_burst, afi_mrnk_write and afi_mrnk_read. Set this to: - 2
RW 0x0
25:24 cfg_dbc0_slot_offset
Enables afi information to be offset by numbers of FR cycles. Affected afi signal is afi_rdata_en, afi_rdata_en_full, afi_wdata_valid, afi_dqs_burst, afi_mrnk_write and afi_mrnk_read. Set this to: - 2
RW 0x0
23:22 cfg_ctrl_slot_offset
Enables afi information to be offset by numbers of FR cycles. Affected afi signal is afi_rdata_en, afi_rdata_en_full, afi_wdata_valid, afi_dqs_burst, afi_mrnk_write and afi_mrnk_read. Set this to: - 2
RW 0x0
21:19 cfg_dbc3_slot_rotate_en
DBC3 slot rotate enable: bit[0] controls write, 1
RW 0x0
18:16 cfg_dbc2_slot_rotate_en
DBC2 slot rotate enable: bit[0] controls write, 1
RW 0x0
15:13 cfg_dbc1_slot_rotate_en
DBC1 slot rotate enable: bit[0] controls write, 1
RW 0x0
12:10 cfg_dbc0_slot_rotate_en
DBC0 slot rotate enable: bit[0] controls write, 1
RW 0x0
9:7 cfg_ctrl_slot_rotate_en
Cmd slot rotate enable: bit[0] controls write, 1
RW 0x0
6:5 cfg_pingpong_mode
Ping Pong mode: 2
RW 0x0
4:0 cfg_tile_id
Tile ID
RW 0x0