Module Instance | Base Address | Register Address |
---|---|---|
i_io48_hmc_mmr_io48_mmr | 0xFFCFA000 | 0xFFCFA044 |
Offset: 0x44
Access: RW
Bit Fields | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
cfg_wb_reserved_entry 0x0 |
cfg_rb_reserved_entry 0x0 |
cfg_clkgating_en 0x0 |
Bit | Name | Description | Access | Reset |
---|---|---|---|---|
14:8 | cfg_wb_reserved_entry | Specify how many enties are reserved in write buffer before almost full is asserted |
RW | 0x0 |
7:1 | cfg_rb_reserved_entry | Specify how many enties are reserved in read buffer before almost full is asserted |
RW | 0x0 |
0 | cfg_clkgating_en | Set to 1 to enable the clock gating. The clock is shut off for the whole HMC |
RW | 0x0 |