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Intel® Xeon® Processor 5600 Series Specification Update

Intel® Xeon® Processor 5600 Series Specification Update

This document is an update to the specifications contained in the Affected Documents table. This document is a compilation of device and documentation errata, specification clarifications, and changes. It is intended for hardware system manufacturers and software developers of applications, operating systems, or tools.

Informati...on types defined in Nomenclature are consolidated into the specification update and are no longer published in other documents. This document may also contain information that was not previously published.

BD1. The Processor may report a #TS instead of a #GP fault problem: A jump to a busy TSS (Task-State Segment) may cause a #TS (invalid TSS exception) instead of a #GP fault (general protection exception).

Implication: Operation systems that access a busy TSS may get invalid TSS fault instead of a #GP fault. Intel has not observed this erratum with any commercially available software.

Workaround: None identified.

Status: For the steppings affected, see the Summary Table of Changes

BD2. REP MOVS/STOS executing with fast strings enabled and crossing page boundaries with inconsistent memory types may use an incorrect data size or lead to memory-ordering violations

Problem: Under certain conditions as described in the Software Developers Manual section "Out-of-Order Stores For String Operations in Pentium® 4, Intel® Xeon®, and P6 Family Processors" the processor performs REP MOVS or REP STOS as fast strings. Due to this erratum fast string REP MOVS/REP STOS instructions that cross page boundaries from WB/WC memory types to UC/WP/WT memory types, may start using an incorrect data size or may observe memory ordering violations.

Read the full Intel® Xeon® Processor 5600 Series Specification Update.

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