Get the Intel® Itanium® Architecture Software Developers' Manual. It is a comprehensive reference manual which contains detailed architectural information to enable development of application software, system software, and software tools for the Itanium processor family.
To obtain bound copies of the "Intel® Itanium® Architecture Software Developer's Manual," please call the Intel Literature Center at 1-800-548-4725 and request order numbers 245317-004 for Volume 1, 245318-004 for Volume 2, and 245319-004 for Volume 3. These volumes are expected to be available for order after November 18, 2012.
A Formal Specification of Intel® Itanium® Processor Family Memory Ordering presents a formal and precise specification of the memory ordering properties for Intel Itanium processor family processors. It contains a new definitional framework for Itanium architecture-based platforms, that is also flexible and able to express memory ordering properties of most known multiprocessors. Memory ordering (also called memory consistency) is a property of shared-memory multiprocessors in which data can be distributed or replicated in different locations.
The Intel® Itanium® 2 Processor Reference Manual for Software Development and Optimization describes microarchitectural details of the Intel Itanium 2 processor, including cache hierarchies, memory management, and instruction execution latencies to enable development of high performance software. It is targeted for developers of compilers and performance software. It contains information regarding optimization via performance monitoring events for the Intel Itanium 2 processor.
The Intel® Itanium® Processor Reference Manual for Software Optimization contains microarchitectural details of the Intel Itanium processor. This document describes features relevant to developers of compilers and performance software. The document contains detailed information including cache hierarchies, memory management, and instruction execution latencies. It also describes performance monitoring events of the Intel Itanium processor to support optimization.
Through Intel Press, Intel® Itanium® Architecture for Software Developers is available. It is a hard-cover book which enables the expert and the novice alike to understand the architecture.
The Floating-Point Software Assistance handler (FPSWA) document describes floating-point exceptions in the architecture and also provides specific details of floating-point software assistance exceptions. This document is useful for operating system writers and other audiences interested in understanding the details of floating point exception handling in the Itanium architecture.
The Itanium® Software Conventions and Runtime Architecture Guide provides the general information necessary to compile, link, and execute a program on an Itanium architecture-based operating system.
The Itanium® Processor-specific Application Binary Interface (ABI) (PDF 705KB) provides further details to address UNIX* software conventions for the Itanium Processor Family. This document provides binary file formats, dynamic linking and low level initialization information for a wide range of UNIX operating systems on the architecture.
Software developers can develop applications using high-level programming languages and depend on Itanium architecture-based compilers for optimization. However, when developers do need to program in assembly language they should refer to the Assembly Language Reference Guide. This document provides details on syntax and conventions used to write Itanium architecture-based standard conforming assembly language.
Assembler conforming source code for the Itanium architecture-based code syntax is now available to software developers in the Itanium® Assembler (iAS). It is intended to serve as a reference implementation for the Assembly Language Reference Guide. The Itanium® Assembler User's Guide describes the usage of the iAS.
The Intel® Itanium® Processor Family Interrupt Architecture Guide is a guide for the Intel® Itanium® architecture Streamlined Advanced Programmable Interrupt Controller (SAPIC). SAPIC is the high performance interrupt architecture for the Intel Itanium architecture. This guide describes the Intel Itanium architecture SAPIC and platform level implementation considerations. It is intended for platform hardware architects (both component and platform) as well as platform software architects (operating system and platform firmware).