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Enhanced MCA Logging in Future Intel® Xeon® Processors

White Paper: Provides usage models, software flows, and reporting mechanisms for enhanced MCA logging and I/O MCA in future Intel® Xeon® processors.

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Intel® 64 and IA-32 Architectures Developer's Manual: Vol. 2A

Architectures Software Developer's Manual: Intel® 64 and IA-32, Vol. 2A: instruction set reference, A-M

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Intel® 64 and IA-32 Architectures Developer's Manual: Vol. 2B

Architectures Software Developer's Manual: Intel® 64 and IA-32, Vol. 2B: instruction set reference, N-Z.

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Intel® 64 and IA-32 Architectures Developer's Manual: Vol. 3A

Architectures Software Developer's Manual: Intel® 64 and IA-32, Vol. 3A: System Programming Guide, Pt 1.

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Intel® 64 and IA-32 Architectures Software Developer’s Manual V2

Volume 2: Instruction Set Reference describes the architecture and programming environment of all Intel® 64 and IA-32 architecture processors.

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Intel® 64 and IA-32 Architectures Developer's Manual: Vol. 2C

Developer's Manual, Vol. 2C, Instruction Set Reference: Intel® 64 and IA-32 Architectures.

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Intel® Itanium® Processor Software Specifications

Intel® Itanium® Processor Software Specifications

I/O Considerations for Server Blades, Backplanes, and Data Centers

Discusses modular computing objectives and identifies the emerging I/O properties necessary to achieve those goals.

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Intel® Many Integrated Core Architecture - Advanced

Intel® Many Integrated Core (Intel® MIC) architecture is the latest breakthrough in supercomputing speed, performance, and compatibility.

Intel® Platform Innovation Framework for EFI—CSM Spec, Rev. 96

Revision 0.96: high-level design of the Compatibility Support Module code to implement the Intel® Platform Innovation Framework for EFI.

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