The visual features built into the processor deliver everything you need to enjoy a stunning and seamless experience when viewing content on your PC.
Simplify two-factor VPN authentication with Intel® IPT with one-time password, removing the need for a separate physical token for no delays.
Simplify the two-factor VPN authentication process with Intel® Identity Protection Technology with one-time password, removing the need for separate physical tokens for a seamless, delay-free experience.
Video: Intel presents Cedar Trail next-gen Atom™ platform at IDF 2011.
Intel presents Cedar Trail Atom™ platform at IDF 2011Full View >
Klocwork* analyzes source code and inspects codebase before Intel® architecture migration, minimizing cost, effort, and complexity. (v.001, Oct. 2011)
Klocwork* provides a comprehensive source code analysis solution and complete codebase inspection prior to embedded Intel® architecture migration, minimizing concerns of cost, effort, and complexity. (v.001, Oct. 2011)Full View >
Gate Dielectric Scaling for High-Performance CMOS: SiO2 to High-K, an option for the 45nm high-performance logic technology node.
Intel demonstrates high-performance PMOS and NMOS transistors with high-K/metal-gate gate stacks with the right threshold voltages for both p- and nchannels on bulk Si
Demonstrates a Germanium p-channel QWFET with thin scaled TOXE and high mobility, delivering four times higher hole mobility.
Paper demonstrates a Germanium p-channel QWFET with thin scaled TOXE and high mobility, delivering four times higher hole mobility reported for any Germanium device than new strained silicon.
Paper: n-type and p-type metal electrodes on high-K gate dielectrics enable same oxide thickness, desirable transistor threshold, and more.
Covers n-type and p-type metal electrodes on high-K gate dielectrics for CMOS applications, enabling metal equivalent oxide thickness with little gate oxide leakage, desirable transistor threshold, and transistor channel mobility similar to SiO2.
Paper: composite high-K gate in the QWFET silicon substrate integration for thin electrical oxide, low gate leakage, and carrier confinement.
Paper covers integration of an advanced composite high-K gate stack in the QWFET silicon substrate, enabling thin electrical oxide, low gate leakage, effective carrier confinement, and high carrier velocity in the QW channel.