Application Note: Interrupt swizzling solution for Intel® 5000 series chipset-based platforms.
Details the interrupt swizzling scheme and the programming and implementation requirements for the Intel® 5000 series chipset.
Thermal and Mechanical Design Guide: Intel® 5000 Series Chipset Memory Controller Hub.
Discusses packaging technology, thermal specification, metrology, and solution for the Intel® 5000 series Chipset Memory Controller Hub.
Datasheet: Intel® 631xESB/ 632xESB I/O Controller Hub covers signal and functional descriptions, mechanical specifications, registers, and more.
This specification is intended for Original Equipment Manufacturers designing and building Intel® 631xESB/632xESB I/O Controller Hub-based products.
Specification Update, 2009: Intel® 631xESB / 632xESB I/O Controller Hub (ESB2), device and document errata and specification changes.
Intel® 631xESB / 632xESB I/O Controller Hub (ESB2), device and document errata and specification changes.
This document is a core specification for a Fully Buffered DIMM (FB DIMM, also FBD) memory system. Information critical to an Intel® 6400/6402 Advanced Memory Buffer (AMB) design appears in the other specifications, with specific cross-references.
Intel® 5000P Chipset for the Intel® Xeon® processor 5000 series can enable a system designer to offer platforms with increased productivity.
The Intel® 5000P Chipset offers increased graphics performance, reduced power consumption, and improved platform reliability and system manageability.
Thermal and Mechanical Design Guide: Intel® 631xESB and 632xESB I/O Controller Hub.
Discusses packaging technology, thermal specification, metrology, and solution for the Intel® 631xESB and 632xESB I/O Controller Hub.