The browser version you are using is not recommended for this site.Please consider upgrading to the latest version of your browser by clicking one of the following links.
We are sorry, This PDF is available in download format only
PHY Interface for PCI Express*, SATA, and USB Specification V4.3IntroductionThe PHY Interface for the PCI Express* (PIPE), SATA, and USB architectures is intended to enable the development of functionally equivalent PCI Express, SATA, and USB PHYs. Such PHYs can be delivered as discrete ICs or as macrocells for inclusion in ASIC designs. The specification defines a set of PHY functions which must be incorporated in a PIPE-compliant PHY, and it defines a standard interface between such a PHY and a media access control (MAC) layer and link layer ASIC. It is not the intent of this specification to define the internal architecture or design of a compliant PHY chip or macrocell. The PIPE specification is defined to allow various approaches to be used. Where possible, the PIPE specification references the PCI Express base specification, SATA 3.0 specification, or USB 3.1 specification rather than repeating its content. In case of conflicts, the PCI-Express Base specification, SATA 3.0 specification, and USB 3.1 specification shall supersede the PIPE specification.Read the full PHY Interface for PCI Express*, SATA, and USB Specification V4.3.
Clalit uses Intel® Xeon® processors to help its health organization provide improved patient care.
Columbia Sportwear deploys an Intel® processor-based VMware virtualization cloud with Vblock*.
Video: The COSMOS Consortium at the University of Cambridge studies how the world began using a supercomputer powered by the Intel® Xeon® processor 7500 series.
Intel® Xeon® processor E5 family-based HPC enables engineering and science simulation, modeling.
GM leaders discuss rapid data sharing to bring vehicles to market faster and increase sales.
Arizona State University’s high performance computing center delivers exceptional capability with Intel® Xeon® processors.