Schematic Review Service
Get your design schematics analyzed for defects and save board spins
This schematic review service1 is available free of charge to users with Privileged Registration who are designing embedded systems and applications. If you are not currently a Privileged User you may register now.
As part of this service, the design schematics is analyzed for compliance with known design guidelines and will report any potential issues back to you.
To enable a schematic review, you must provide the following:
Design files in one of the following formats:
a. Cadence Allegro* Board/MCM File version 14.x, 15.x, 16.x (*.BRD or *.MCM)
b. Cadence Concept* HDL Packaged Schematic Files up to version 16.x (pstxref.dat, pstchip.dat, and pstxprt.dat)
c. Cadence OrCAD* Capture Schematic Files version 9.2, 10.x or 16.x (Non-hierarchical: *.EDF, Hierarchical: pstxprt.dat, pstchip.dat, and pstxnet.dat)
d. Mentor Expedition* Exported EDIF Schematic Files version 16.x (*.EDF)
e. Zuken Design Gateway* Exported EDIF Schematic Files version 8.000, 8.010 (*.EDF, [Versions between 8.000 and 2012.100 are not supported])
f. Zuken Design Gateway* Exported ISCF Schematic Files version 2012.100 or newer (*.ISCF [Preferred Format])
g. Zuken System Designer* Exported EDIF Schematic Files version 13.0 (*.EDF [Versions between 13.0 and 15.0 are not supported])
h. Zuken System Designer* Exported ISCF Schematic Files version 15.0 or newer (*.ISCF [Preferred Format])
i. Mentor Expedition* Exported EDIF Schematic Files version EE2007.x (*.EDF or *.HKP)
Note: Ensure that the “Generate flat EDIF Netlist” option is selected if providing a Mentor .EDF file from Design Capture or Design View. For DxDesigner, use Schematic EDIF Generation (Schematic Writer). Optional License Required for Schematic Writer (220524 EDIF 200 Graphics I/F Op SW). Design Capture can also use Schematic Writer.
Schematics in .PDF format, searchable with x-y coordinates and off-page references
a. This Must correspond to the associated schematic file
b. Match the net names for the processor and chipset pins with those listed in the respective datasheets. If the net names are not identical, please submit a spreadsheet using the same net names as the datasheet. (As an option, please provide a list of the net names of the Standby, Resume, Always On voltage nets).
High-level block diagram of schematic design
(Separate document optional: can be included in schematics file required in 2 above.)
a. Platform name and Processor being used
b. Page number references per block that correspond to the schematic pages
We also recommend you provide a list of the Intel Device Name with your equivalent Reference Designator for the major Intel components in the design, along with a list of No Stuff/Unplaced/No Fit components and notes on configurations of interfaces, such as mode of operation of displays etc.
Intel will make every effort to provide you with a final report within five business days from submission of all the material, frequently completing the report much sooner.
1. This service does not replace a customer’s in-house schematic review, nor is it a substitute for training in design or knowledge of basic Intel® architecture. Although Intel makes a good faith effort to find potential design problems, the customer remains responsible for the success of the design. The results of the schematic review are suggestions from Intel based on Intel’s experience and knowledge, and may be accepted or rejected. Each company is ultimately responsible for determining the suitability of its own design and is responsible for the quality of its products. Intel makes no claims or guarantees that the Intel reviewers will find all defects, or that the design will function in accordance to the customer’s requirements. Neither does Intel accept responsibility for any impact to the customer’s project schedules.