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82547GI/82547EI Gigabit Ethernet Controller Networking Silicon Datasheet Product Features

■ CSA Port — PCI-X revision 1.0a, up to 133 MHz — Uses dedicated port for clientLAN controller directly on MCH device — High-speed interface with twice the peak bandwidth of 32-bit, 33 MHz PCI bus — PCI power management registers by MCH ■ ■ MAC Specific — Optimized transmit and receive queues — IEEE 802.3x-compliant flow-control support with software-controllable thresholds — Caches up to 64 packet descriptors in a single burst — Programmable host memory receive buffers (256 B to 16 KB) and cache line size (16 B to 256 B) — Wide, optimized internal data path architecture ■ — 40 KB configurable Transmit and Receive FIFO buffers — Descriptor ring management hardware for transmit and receive — Optimized descriptor fetching and write- back mechanisms ■ — Mechanism available for reducing interrupts generated by transmit and receive operations — Support for transmission and reception of packets up to 16 KB ■ PHY Specific — Integrated for 10/100/1000 Mb/s full- and ■ half-duplex operation — IEEE 802.3ab Auto-Negotiation and PHY compliance and compatibility a. This device is lead-free. That is, lead has not been <1000 ppm. The Material Declaration Data Sheet, which Restriction on Hazardous Substances (RoHS)-banned In addition, this device has been tested and conforms to the the device. For more information regarding lead-free products from tative — State-of-the-art DSP architecture implements digital adaptive equalization, echo and cross- talk cancellation —PHY cable correction and diagnostics —Automatic detection of cable lengths and MDI vs. MDI-X cable at all speeds Host Off-Loading — Transmit and receive IP, TCP, and UDP checksum off-loading capabilities — Transmit TCP segmentation and advanced packed filtering — IEEE 802.1Q VLAN tag insertion and stripping and packet filtering for up to 4096 VLAN tags — Jumbo frame support up to 16 KB — Intelligent Interrupt generation (multiple packets per interrupt) Manageability — On-chip SMBus 2.0 port — ASF 1.0 and 2.0 — Compliance with PCI Power Management v1.1/ACPI v2.0 — Wake on LAN* (WoL) support Additional Device — Four programmable LED outputs — On-chip power regulator control circuitry — BIOS LAN Disable pin — JTAG (IEEE 1149.1) Test Access Port built in silicon a Lead-free 196-pin Ball Grid Array (BGA). Devices that are lead-free are marked with a circled “e1” and have the product code: LUxxxxxx. intentionally added, but lead may still exist as an impurity at includes lead impurity levels and the concentration of other materials, is available at: ftp://download.intel.com/design/packtech/material_content_IC_Package.pdf#pagemode=bookmarks same parametric specifications as previous versions of Intel Corporation, contact your Intel Field Sales represen- Revision 2.1 November 2004 Revision History Date Aug 2003 Nov 2004 Revision 2.0 2.1 Notes Non-classified release. • Added Architecture Overview chapter. • Update signal names to match Design Guide and EEPROM Map and Programming Application Note. • Updated lead-free information. • Added information about migrating from a 2-layer 0.36 mm wide-trace substrate to a 2-layer 0.32 mm wide-trace substrate. Refer to the sec- tion on Package and Pinout Information. • Added statement that no changes to existing soldering processes are Read the full 82547GI/82547EI Gigabit Ethernet Controller Networking Silicon Datasheet Product Features.

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