Product Features Datasheet ■ PCI Bus — PCI Revision 2.3 support for 32-bit wide interface at 33 MHz and 66 MHz — Algorithms that optimally use advanced PCI, MWI, MRM, and MRL commands — CardBus Information Services (CIS) Pointer —CLK_RUN# Signal ■ MAC Specific — Low-latency transmit and receive queues — IEEE 802.3x-compliant flow-control support with software-controllable thresholds — Caches up to 64 packet descriptors in a single burst — Programmable host memory receive buffers (256 B to 16 KB) and cache line size (16 B to 256 B) — Wide, optimized internal data path architecture — 64 KB configurable Transmit and Receive FIFO buffers ■ PHY Specific — Integrated for 10/100/1000 Mb/s operation — IEEE 802.3ab Auto-Negotiation support — IEEE 802.3ab PHY compliance and compatibility. State-of-the-art DSP architecture implements digital adaptive equalization, echo cancellation, and cross- talk cancellation — Automatic detection of cable lengths and MDI vs. MDI-X cable at all speeds ■ Host Off-Loading — Transmit and receive IP, TCP, and UDP checksum off-loading capabilities — Transmit TCP segmentation — Advanced packed filtering — Jumbo frame support up to 16 KB — IEEE 802.1q VLAN support with VLAN tag insertion, stripping and packet filtering for up to 4096 VLAN tags — Descriptor ring management hardware for transmit and receive — Interrupt coalescing (multiple packets per interrupt) ■ Manageability — Manageability features: Onboard SMB port, ASF 1.0, ACPI, Wake on LAN, and PXE — Compliance with PCI Power Management 1.1 and ACPI 2.0 register set compliant —SNMP and RMON statistic counters —SDG 3.0, WfM 2.0, and PC2001 compliance ■ Additional Device — Four activity and link indication outputs that directly drive LEDs — JTAG (IEEE 1149.1) Test Access Port built in silicon — Internal PLL for clock generation can use a 25 MHz crystal — Programmable LED functionality — Industrial temperature support (-40 to °C) +85 317887-002 Revision 2.0 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel products referenced in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact Read the full 82540EP Gigabit Ethernet Controller Networking Silicon.