Intel® 5000V Chipset
The Intel® 5000V chipsets for the Intel® Xeon® processor 5000 series enable Intel® dual-processor (DP) balanced server platforms that are efficient, dependable, and responsive.
Intel® dual-core processor-based platforms help businesses better utilize assets with effective virtualization and increase density in their data centers through optimized power and thermal features.
The dual-core processor servers offer increased value to enterprise front-end, small to medium business (SMB), and high performance computing (HPC) applications.
|Features and benefits|
|Supports two Intel® Xeon® processors 5000 series||Optimized performance for the DP Server market segment with a range of price points.|
|1066 / 1333 MHz dual independent buses||Increased bus bandwidth of up to 3X over 800 MHz systems.|
|FB DIMM 533/667 MHz memory interface||Offers a maximum memory bandwidth up to 8.5 GB/s for 533 MHz and 10.5 GB/s for 667 MHz.
Increased dual in-line memory modules (DIMMs) per system provide enhanced memory scalability for memory-intensive applications.
|PCI Express* I/O||Serial I/O technology provides a direct connection between the MCH chipset and PCI Express* component/adapters with bandwidth up to 4 GB/s on each PCI Express x8 interface. PCI Express offers higher bandwidth, lower latency and fewer I/O bottlenecks than PCI-X.|
|Optional component introduces next-generation PCI/PCI-X performance and significant enhancements to platform flexibility.
Supports two independent 64-bit, 133 MHz PCI-X segments and two Hot-Plug controllers (one per segment).
|Features such as memory Error Correction Code (ECC), Intel® x4 Single Device Data Correction (x4 SDDC), DIMM sparing and DIMM scrubbing for improved system reliability.
The System Management Bus (SMBus) hooks into the Intel® 5000V MCH chipset for remote management operation and support for a variety of third-party base management controller (BMC) and BIOS solutions.
|Intel® 5000V Memory Controller Hub (MCH) chipset||1432 Flip Chip-Ball Grid Array (FC-BGA)|
|Intel® 6700PXH 64-bit PCI Hub||567 Flip Chip-Ball Grid Array (FC-BGA)|
|Intel® 6321ESB I/O Controller Hub||1284 Flip Chip - Ball Grid Array (FC-BGA)|
Additional information: 1 2 3 4
1. The 1333 MHz system bus feature will be available in the second half of 2006.
2. Intel® processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See www.intel.com/content/www/us/en/processors/processor-numbers.html for details.
3. PCI Express* reduced power-state "L0s" is not supported.
4. In an x4 DDR memory device, the Intel® x4 Single Device Data Correction (x4 SDDC) provides error detection and correction for 1, 2, 3 or 4 data bits within that single device and provides error detection, up to 8 data bits, within two devices.